EN25Q64-104FIP datasheet(25/60 Pages) EON

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EN25Q64

Rev. J, Issue Date: 2011/07/07

Read Data Bytes (READ) (03h)

The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the

rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial

Data Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling edge of

Serial Clock (CLK).

The instruction sequence is shown in Figure 11. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out.

The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When

the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select

(CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction,

while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the

cycle that is in progress.

Figure 11. Read Data Instruction Sequence Diagram

Read Data Bytes at Higher Speed (FAST_READ) (0Bh)

The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data

Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a

dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory

contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a

maximum frequency FR, during the falling edge of Serial Clock (CLK).

The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out.

The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed

(FAST_READ) instruction. When the highest address is reached, the address counter rolls over to

000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select

(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes

at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.

The instruction sequence is shown in Figure 12.1 while using the Enable Quad Peripheral Interface mode

(EQPI) (38h) command.

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