EN25Q64-104FIP datasheet(34/60 Pages) EON

34 / 60 page

This Data Sheet may be revised by subsequent versions

www.eonssi.com

or modifications due to changes in technical specifications.

EN25Q64

Rev. J, Issue Date: 2011/07/07

Figure 17.1 Program Instruction Sequence under EQPI Mode

Sector Erase (SE) (20h)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write

Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the in-

struction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see

Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low

for the entire duration of the sequence.

The instruction sequence is shown in Figure 18. Chip Select (CS#) must be driven High after the eighth

bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not

executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read

to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the

self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle

is completed, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP3, BP2,

BP1, BP0) bits (see Table 3) is not executed.

The instruction sequence is shown in Figure 19.1 while using the Enable Quad Peripheral Interface mode

(EQPI) (38h) command.

EN25Q64-104FIP bảng dữ liệu(PDF) 34 Page - Eon Silicon Solution Inc.