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EN25Q64-104FIP bảng dữ liệu(PDF) 19 Page - Eon Silicon Solution Inc. |
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EN25Q64-104FIP bảng dữ liệu(HTML) 19 Page - Eon Silicon Solution Inc. |
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19 / 60 page ![]() This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 19 EN25Q64 Rev. J, Issue Date: 2011/07/07 Software Reset Flow Initial Command = 66h ? Reset enable Command = 99h ? Reset start WIP = 0 ? Reset done Embedded Reset Cycle Yes No No Yes No Yes Note: 1. Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) commands need to match standard SPI or EQPI (quad) mode. 2. Continue (Enhance) EB mode need to use quad Reset-Enable (RSTEN) (66h) and quad Reset (RST) (99h) commands. 3. If user is not sure it is in SPI or Quad mode, we suggest to execute sequence as follows: Quad Reset-Enable (RSTEN) (66h) -> Quad Reset (RST) (99h) -> SPI Reset-Enable (RSTEN) (66h) -> SPI Reset (RST) (99h) to reset. 4. The reset command could be executed during embedded program and erase process, EQPI mode and Continue EB mode to back to SPI mode. 5. This flow cannot release the device from Deep power down mode. 6. The Status Register Bit will reset to default value after reset done. 7. If user reset device during erase, the embedded reset cycle software reset latency will take about 28us in worst case. |
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