EN25Q64-104FIP datasheet(28/60 Pages) EON

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EN25Q64

Rev. J, Issue Date: 2011/07/07

Dual Input / Output FAST_READ (BBh)

The Dual I/O Fast Read (BBh) instruction allows for improved random access while maintaining two IO

pins, DQ0 and DQ1. It is similar to the Dual Output Fast Read (3Bh) instruction but with the capability to

input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code

execution (XIP) directly from the Dual SPI in some applications.

The Dual I/O Fast Read instruction enable double throughput of Serial Flash in read mode. The

address is latched on rising edge of CLK, and data of every two bits (interleave 2 I/O pins) shift out on

the falling edge of CLK at a maximum frequency. The first address can be at any location. The address

is automatically increased to the next higher address after each byte data is shifted out, so the whole

memory can be read out at a single Dual I/O Fast Read instruction. The address counter rolls over to 0

when the highest address has been reached. Once writing Dual I/O Fast Read instruction, the following

address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in Figure 14.

Figure 14. Dual Input / Output Fast Read Instruction Sequence Diagram

“Quad Input / Output FAST_READ (EBh)

The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh)

instruction except that address and data bits are input and output through four pins, DQ0, DQ1, DQ2 and

DQ3 and six Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces

instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.

The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read

mode. The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O

pins) shift out on the falling edge of CLK at a maximum frequency FR. The first address can be any

location. The address is automatically increased to the next higher address after each byte data is

shifted out, so the whole memory can be read out at a single Quad Input/Output FAST_READ

instruction. The address counter rolls over to 0 when the highest address has been reached. Once

writing Quad Input/Output FAST_READ instruction, the following address/dummy/data out will perform

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