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EN25Q64-104FIP bảng dữ liệu(PDF) 60 Page - Eon Silicon Solution Inc. |
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EN25Q64-104FIP bảng dữ liệu(HTML) 60 Page - Eon Silicon Solution Inc. |
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60 / 60 page ![]() This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 60 EN25Q64 Rev. J, Issue Date: 2011/07/07 Revisions List Revision No Description Date F 1. Add 8-pin PDIP package option 2. Add 24-ball Ball Grid Array (6 x 8 mm) package option 3. For the dual and quad SPI, change the speed from 50MHz to 80MHz. 4. Remove Write Suspend and Write Resume information. 5. Modify Software Reset Latency from 20µs to 28µs on page 47. 2010/02/05 G 1. Update AC Characteristics in Table 11 on page 47. (1). Sector Erase time from 0.09s to 0.06s (typ.) (2). Block Erase time from 0.5s to 0.3s (typ.) 2010/04/19 H 1. Rename 38h command from Enable Quad I/O (EQIO) to Enable Quad Peripheral Interface mode (EQPI). 2. Revise the speed of Quad SPI from 80MHz to 50MHz. 3. Revise the Chip Erase Time (Max.) from 50s to 70s on page47. 2011/01/10 I 1. Update Write Status Register Cycle Time from 10 (typ.) /15 (max.) ms to 15 (typ.) / 50 (max.) ms on page 47. 2. Rename 24 Ball package from BGA to TFBGA. 2011/04/18 J 1. Add the note “5. This flow cannot release the device from Deep power down mode.” on page 19. 2. Correct the typo of 6 dummy clocks for EBh command on page 28. 2011/07/07 |
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