EN25Q64-104FIP datasheet(22/60 Pages) EON

22 / 60 page

This Data Sheet may be revised by subsequent versions

www.eonssi.com

or modifications due to changes in technical specifications.

EN25Q64

Rev. J, Issue Date: 2011/07/07

Figure 9.1 Read Status Register Instruction Sequence under EQPI Mode

Table 6. Status Register Bit Locations

SRP

Status

Protect

OTP_LOCK

bit

(note 1)

WPDIS

(WP# disable)

BP3

(Block

Protected bits)

BP2

(Block

Protected bits)

BP1

(Block

Protected bits)

BP0

(Block

Protected bits)

WEL

(Write Enable

Latch)

WIP

(Write In

Progress bit)

(Note 3)

1 = status

disable

1 = OTP

sector is

protected

1 = WP#

disable

0 = WP#

enable

(note 2)

1 = write

enable

0 = not write

enable

1 = write

operation

0 = not in write

operation

Non-volatile bit

Non-volatile bit Non-volatile bit. Non-volatile bit Non-volatile bit Non-volatile bit

volatile bit

Note

1. In OTP mode, SRP bit is served as OTP_LOCK bit.

2. See the table “

Protected Area Sizes Sector Organization”.

The status and control bits of the Status Register are as follows:

WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status

cycle is in progress.

WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is

reset and no Write Status Register, Program or Erase instruction is accepted.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define

the size of the area to be software protected against Program and Erase instructions. These bits are

written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,

BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected

against Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect

(BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.

The Chip Erase (CE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1, BP0) bits

are 0.

EN25Q64-104FIP bảng dữ liệu(PDF) 22 Page - Eon Silicon Solution Inc.

EN25Q64-104FIP bảng dữ liệu(HTML) 22 Page - Eon Silicon Solution Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

bảng dữ liệu tải về

Link URL