EN25Q64-104FIP datasheet(33/60 Pages) EON

33 / 60 page

This Data Sheet may be revised by subsequent versions

www.eonssi.com

or modifications due to changes in technical specifications.

EN25Q64

Rev. J, Issue Date: 2011/07/07

Page Program (PP) (02h)

The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be

accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write

Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the in-

struction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least

significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the

current page are programmed from the start address of the same page (from the address whose 8

least significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration

of the sequence.

The instruction sequence is shown in Figure 17. If more than 256 bytes are sent to the device, pre-

viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor-

rectly within the same page. If less than 256 Data bytes are sent to device, they are correctly pro-

grammed at the requested addresses without having any effects on the other bytes of the same page.

Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in,

otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is tPP)

is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the

value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page

Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,

the Write Enable Latch (WEL) bit is reset.

A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3, BP2,

BP1, BP0) bits (see Table 3) is not executed.

The instruction sequence is shown in Figure 17.1 while using the Enable Quad Peripheral Interface mode

(EQPI) (38h) command.

Figure 17. Page Program Instruction Sequence Diagram

EN25Q64-104FIP bảng dữ liệu(PDF) 33 Page - Eon Silicon Solution Inc.