LPC64 datasheet(52/65 Pages) NXP

tên linh kiện	LPC64

Giải thích chi tiết về linh kiện	32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN

PDF	65 Pages

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nhà sản xuất	NXP [NXP Semiconductors]

Trang chủ	http://www.nxp.com

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52 / 65 page

LPC1768_67_66_65_64_3

Product data sheet

Rev. 03 — 19 November 2009

52 of 65

NXP Semiconductors

LPC1768/67/66/65/64

32-bit ARM Cortex-M3 microcontroller

11.8 SPI

[1]

TSPICYC = (Tcy(PCLK) × n) ± 0.5 %, n is the SPI clock divider value (n ≥ 8); PCLK is derived from the

processor clock CCLK.

[2]

Timing parameters are measured with respect to the 50 % edge of the clock SCK and the 10 % (90 %)

edge of the data signal (MOSI or MISO).

Table 14.

Dynamic characteristics of SPI pins

Tamb = −40 °C to +85 °C.

Symbol

Parameter

Min

Typ

Max

Unit

Tcy(PCLK)

PCLK cycle time

TSPICYC

SPI cycle time

[1]

79.6

tSPICLKH

SPICLK HIGH time

0.485

× T

SPICYC

tSPICLKL

SPICLK LOW time

0.515

× T

SPICYC

SPI master

tSPIDSU

SPI data set-up time

[2]

tSPIDH

SPI data hold time

[2]

× T

cy(PCLK) − 5

tSPIQV

SPI data output valid time

[2]

× T

cy(PCLK) + 30

tSPIOH

SPI output data hold time

[2]

× T

cy(PCLK) + 5

SPI slave

tSPIDSU

SPI data set-up time

[2]

tSPIDH

SPI data hold time

[2]

× T

cy(PCLK) + 5

tSPIQV

SPI data output valid time

[2]

× T

cy(PCLK) + 35

tSPIOH

SPI output data hold time

[2]

× T

cy(PCLK) + 15

Fig 17.

SPI master timing (CPHA = 1)

SCK (CPOL = 0)

MOSI

MISO

002aad986

TSPICYC

tSPICLKH

tSPICLKL

tSPIDSU

tSPIDH

tSPIQV

DATA VALID

tSPIOH

SCK (CPOL = 1)

DATA VALID

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