LPC64 datasheet(35/65 Pages) NXP

35 / 65 page

LPC1768_67_66_65_64_3

Product data sheet

Rev. 03 — 19 November 2009

35 of 65

NXP Semiconductors

LPC1768/67/66/65/64

32-bit ARM Cortex-M3 microcontroller

7.29.8 Power domains

The LPC17xx provide two independent power domains that allow the bulk of the device to

have power removed while maintaining operation of the RTC and the backup Registers.

On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the

VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the

CPU and most of the peripherals.

Depending on the LPC17xx application, a design can use two power options to manage

power consumption.

The first option assumes that power consumption is not a concern and the design ties the

VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not

support powering down the I/O pad ring “on the fly” while keeping the CPU and

peripherals alive.

The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and

a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator

powered independently from the I/O pad ring enables shutting down of the I/O pad power

supply “on the fly”, while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of

power to operate, which can be supplied by an external battery. The device core power

(VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore,

there is no power drain from the RTC battery when VDD(REG)(3V3) is available.

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