LPC64 datasheet(38/65 Pages) NXP

38 / 65 page

LPC1768_67_66_65_64_3

Product data sheet

Rev. 03 — 19 November 2009

38 of 65

NXP Semiconductors

LPC1768/67/66/65/64

32-bit ARM Cortex-M3 microcontroller

7.30.5 AHB multilayer matrix

The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code)

and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main

(32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these

memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM

blocks. Additionally, the matrix connects the CPU system bus and all of the DMA

controllers to the various peripheral functions.

7.30.6 External interrupt inputs

The LPC17xx include up to 46 edge sensitive interrupt inputs combined with up to four

level sensitive external interrupt inputs as selectable pin functions. The external interrupt

inputs can optionally be used to wake up the processor from Power-down mode.

7.30.7 Memory mapping control

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address

space. The vector table must be located on a 128 word (512 byte) boundary because the

NVIC on the LPC17xx is configured for 128 total interrupts.

7.31 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four

watch points.

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