LPC64 datasheet(48/65 Pages) NXP

48 / 65 page

LPC1768_67_66_65_64_3

Product data sheet

Rev. 03 — 19 November 2009

48 of 65

NXP Semiconductors

LPC1768/67/66/65/64

32-bit ARM Cortex-M3 microcontroller

11.4 I2C-bus

[1]

Parameters are valid over operating temperature range unless otherwise specified.

[2]

CCLK = PCLK = 20 MHz; I2C-bus interface configured in master mode.

[3]

Bus capacitance Cb in pF (50 pF), external pull-up resistance = 218 Ω.

11.5 I2S-bus interface (LPC1768/67/66/65 only)

[1]

CCLK = 20 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK

⁄

4; I

2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK

signal in the I2S-bus specification.

Table 10.

Dynamic characteristic: I2C-bus pins (Fast-mode Plus)

Tamb = −40 °C to +85 °C; VDD(3V3) over specified ranges.[1][2][3]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCL

SCL clock frequency

MHz

fall time

tSU;DAT

data set-up time

Fig 12. I2C-bus pins clock timing

002aae860

tSU;DAT

SDA

SCL

Table 11.

Dynamic characteristics: I2S-bus interface pins

Tamb = −40 °C to +85 °C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

common to input and output

rise time

[1]

fall time

[1]

tWH

pulse width HIGH

on pins I2STX_CLK and

I2SRX_CLK

[1]

0.495

× T

cy(clk)

tWL

pulse width LOW

on pins I2STX_CLK and

I2SRX_CLK

[1]

0.505

× T

cy(clk)

output

tv(Q)

data output valid time

on pin I2STX_SDA;

[1]

on pin I2STX_WS

[1]

input

tsu(D)

data input set-up time

on pin I2SRX_SDA

[1]

3.5

th(D)

data input hold time

on pin I2SRX_SDA

[1]

4.0

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