LPC64 datasheet(29/65 Pages) NXP

29 / 65 page

LPC1768_67_66_65_64_3

Product data sheet

Rev. 03 — 19 November 2009

29 of 65

NXP Semiconductors

LPC1768/67/66/65/64

32-bit ARM Cortex-M3 microcontroller

• Digital filter with programmable delays for encoder input signals.

• Can accept decoded signal inputs (clk and direction).

• Connected to APB.

7.25 Repetitive Interrupt (RI) timer

The repetitive interrupt timer provides a free-running 32-bit counter which is compared to

a selectable value, generating an interrupt when a match occurs. Any bits of the

timer/compare can be masked such that they do not contribute to the match detection.

The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

7.25.1 Features

• 32-bit counter running from PCLK. Counter can be free-running or be reset by a

generated interrupt.

• 32-bit compare value.

• 32-bit compare mask. An interrupt is generated when the counter value equals the

compare value, after masking. This allows for combinations not possible with a simple

compare.

7.26 ARM Cortex-M3 system tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval. In the LPC17xx, this timer can be

clocked from the internal AHB clock or from a device pin.

7.27 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

7.27.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal prescaler.

• Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 232 × 4) in

multiples of Tcy(WDCLK) × 4.

• The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC)

oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of

potential timing choices of Watchdog operation under different power reduction

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