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LPC64 bảng dữ liệu(PDF) 51 Page - NXP Semiconductors |
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LPC64 bảng dữ liệu(HTML) 51 Page - NXP Semiconductors |
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51 / 65 page ![]() LPC1768_67_66_65_64_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 19 November 2009 51 of 65 NXP Semiconductors LPC1768/67/66/65/64 32-bit ARM Cortex-M3 microcontroller 11.7 USB interface (LPC1768/66/65/64 only) [1] Characterized but not implemented as production test. Guaranteed by design. Table 13. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3), unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.0 V tFEOPT source SE0 interval of EOP see Figure 16 160 - 175 ns tFDEOP source jitter for differential transition to SE0 transition see Figure 16 −2 - +5 ns tJR1 receiver jitter to next transition −18.5 - +18.5 ns tJR2 receiver jitter for paired transitions 10 % to 90 % −9 - +9 ns tEOPR1 EOP width at receiver must reject as EOP; see Figure 16 [1] 40 - - ns tEOPR2 EOP width at receiver must accept as EOP; see Figure 16 [1] 82 - - ns Fig 16. Differential data-to-EOP transition skew and EOP width 002aab561 TPERIOD differential data lines crossover point source EOP width: tFEOPT receiver EOP width: tEOPR1, tEOPR2 crossover point extended differential data to SE0/EOP skew n × TPERIOD + tFDEOP |
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