68HC05P9A datasheet(15/90 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

GENERAL DESCRIPTION

Rev. 2.0

1-5

1.5.3 OSC1 and OSC2

These pins provide control input for an on-chip clock oscillator circuit. A crystal, a

ceramic resonator, a resistor/capacitor combination, or an external signal

connects to these pins and provides a system clock. A mask option selects either

a crystal/ceramic resonator or a resistor/capacitor as the frequency determining

element. The oscillator frequency is two times the internal bus rate.

1.5.4 RESET

This active low pin is used to reset the MCU to a known start-up state by pulling

RESET low. The RESET pin contains an internal Schmitt trigger as part of its

input to improve noise immunity.

1.5.5 TCMP

This pin provides an output for the output compare feature of the on-chip timer

system.

1.5.6 PA0 through PA7

Port A is an 8-bit bidirectional port which does not share any of its pins with other

subsystems. The port A data register is at $0000, and the data direction register is

at $0004. Reset does not affect the data registers, but clears the data direction

registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the

corresponding port bit to output mode. Port A has mask option enabled pullup

devices and interrupt capability by pin. For a detailed description of I/O

programming, refer to 1.6 Input/Output Programming.

Figure 1-3. Port A Pullup Option

PA0

VDD

DDR Bit

Normal Port

From all other Port A pins

IRQ

Schmitt

Trigger

To Interrupt

Logic

Mask Option

Circuitry

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