68HC05P9A datasheet(39/90 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

SIMPLE SERIAL INPUT/OUTPUT PORT

Rev. 2.0

7-1

SECTION 7

SIMPLE SERIAL INPUT/OUTPUT PORT

This device includes a simple synchronous serial I/O port. The SIOP is a three

wire master/slave system including serial clock (SCK), serial data input (SDI), and

serial data output (SDO). A mask programmable option determines whether the

SIOP is MSB or LSB ﬁrst.

7.1

Signal Format

The following paragraphs describe the SIOP signal format.

7.1.1 Serial Clock (SCK)

The state of SCK between transmissions and prior to enabling the SIOP must be

logic one. The ﬁrst falling edge of SCK signals the beginning of a transmission.

At this time, the ﬁrst bit of received data is accepted at the SDI pin and the ﬁrst bit

of transmitted data is presented at the SDO pin. Data is captured at the SDI pin

on the rising edge of SCK. Subsequent falling edges shift the data and accept or

present the next bit. The transmission is ended upon the eighth rising edge of

SCK. The maximum frequency of SCK in slave mode is equal to E (bus clock)

divided by four. That is, for a 4-MHz oscillator input, E becomes 2 MHz and the

maximum SCK frequency is 0.5 MHz. There is no minimum SCK frequency.

Figure 7-1. SIOP Block Diagram

8-BIT SHIFT REGISTER

RESET

SDO

SCK

SDI

MSB/LSB MASK OPTION

DATA BUS

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