HCS12 datasheet(415/452 Pages) FREESCALE

415 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

415

B.7 Improved Performance

The HCS12 uses a system-on-a-chip (SoC) design methodology and is

normally implemented in a 0.25

µ FLASH process. HCS12 devices can

operate at up to 25 MHz and are designed to be migrated easily to faster,

smaller silicon process technologies as they are developed.

The M68HC12 improves on M68HC11 performance in several ways.

M68HC12 devices are designed using sub-micron design rules and

fabricated using advanced semiconductor processing, the same methods

used to manufacture the M68HC16 and M68300 Families of modular

microcontrollers. M68HC12 devices have a base bus speed of 8 MHz and

are designed to operate over a wide range of supply voltages.

The 16-bit wide architecture of the CPU12 also increases performance.

Beyond these obvious improvements, the CPU12 uses a reduced number

of cycles for many of its instructions, and a 20-bit ALU makes certain CPU12

math operations much faster.

B.7.1 Reduced Cycle Counts

No M68HC11 instruction takes less than two cycles, but the CPU12 has

more than 50 opcodes that take only one cycle. Some of the reduction

comes from the instruction queue, which ensures that several program

bytes are available at the start of each instruction. Other cycle reductions

occur because the CPU12 can fetch 16 bits of information at a time, rather

than eight bits at a time.

B.7.2 Fast Math

The CPU12 has some of the fastest math ever designed into a Freescale

general-purpose MCU. Much of the speed is due to a 20-bit ALU that can

perform two smaller operations simultaneously. The ALU can also perform

two operations in a single bus cycle in certain cases.

Table B-3 compares the speed of CPU12 and M68HC11 math instructions.

The CPU12 requires fewer cycles to perform an operation, and the cycle

time is considerably faster than that of the M68HC11.

HCS12 bảng dữ liệu(PDF) 415 Page - Freescale Semiconductor, Inc