HCS12 datasheet(408/452 Pages) FREESCALE

408 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

408

Freescale Semiconductor

B.5.2 Instruction Queue

The CPU12 has a 2-word instruction queue and a 16-bit holding buffer,

which sometimes acts as a third word for queueing program information. All

program information is fetched from memory as aligned 16-bit words, even

though there is no requirement for instructions to begin or end on even word

boundaries. There is no penalty for misaligned instructions. If a program

begins on an odd boundary (if the reset vector is an odd address), program

information is fetched to fill the instruction queue, beginning with the aligned

word at the next address below the misaligned reset vector. The instruction

queue logic starts execution with the opcode in the low-order half of this

word.

The instruction queue causes three bytes of program information (starting

with the instruction opcode) to be directly available to the CPU at the

beginning of every instruction. As it executes, each instruction performs

enough additional program fetches to refill the space it took up in the queue.

Alignment information is maintained by the logic in the instruction queue.

The CPU provides signals that tell the queue logic when to advance a word

of program information and when to toggle the alignment status.

The CPU is not aware of instruction alignment. The queue logic includes a

multiplexer that sorts out the information in the queue to present the opcode

and the next two bytes of information as CPU inputs. The multiplexer

determines whether the opcode is in the even or odd half of the word at the

head of the queue. Alignment status is also available to the ALU for address

calculations. The execution sequence for all instructions is independent of

the alignment of the instruction.

The only situation where alignment can affect the number of cycles an

instruction takes occurs in devices that have a narrow (8-bit) external data

bus and is related to optional program fetch cycles (O type cycles). O cycles

are always performed, but serve different purposes determined by

instruction size and alignment.

Each instruction includes one program fetch cycle for every two bytes of

object code. Instructions with an odd number of bytes can use an O cycle to

fetch an extra word of object code. If the queue is aligned at the start of an

instruction with an odd byte count, the last byte of object code shares a

queue word with the opcode of the next instruction. Since this word holds

part of the next instruction, the queue cannot advance after the odd byte

executes because the first byte of the next instruction would be lost. In this

case, the O cycle appears as a free cycle since the queue is not ready to

accept the next word of program information. If this same instruction had

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