HCS12 datasheet(353/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

353

9.5 REV and REVW Instruction Details

This section provides a more detailed explanation of the rule evaluation

instructions (REV and REVW). The data structures used to specify rules are

somewhat different for the weighted versus unweighted versions of the

instruction. One uses 8-bit offsets in the encoded rules, while the other uses

full 16-bit addresses. This affects the size of the rule data structure and

execution time.

9.5.1 Unweighted Rule Evaluation (REV)

This instruction implements basic min-max rule evaluation. CPU registers

are used for pointers and intermediate calculation results.

Since the REV instruction is essentially a list-processing instruction,

execution time is dependent on the number of elements in the rule list. The

REV instruction is interruptible (typically within three bus cycles), so it does

not adversely affect worst case interrupt latency. Since all intermediate

results and instruction status are held in stacked CPU registers, the interrupt

service code can even include independent REV and REVW instructions.

9.5.1.1 Set Up Prior to Executing REV

Some CPU registers and memory locations need to be set up prior to

executing the REV instruction. X and Y index registers are used as index

pointers to the rule list and the fuzzy inputs and outputs. The A accumulator

is used for intermediate calculation results and needs to be set to $FF

initially. The V condition code bit is used as an instruction status indicator to

show whether antecedents or consequents are being processed. Initially,

the V bit is cleared to zero to indicate antecedents are being processed. The

fuzzy outputs (working RAM locations) need to be cleared to $00. If these

values are not initialized before executing the REV instruction, results will

be erroneous.

The X index register is set to the address of the first element in the rule list

(in the knowledge base). The REV instruction automatically updates this

pointer so that the instruction can resume correctly if it is interrupted. After

the REV instruction finishes, X will point at the next address past the $FF

separator character that marks the end of the rule list.

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