HCS12 datasheet(306/452 Pages) FREESCALE

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Instruction Glossary

S12CPUV2 Reference Manual, Rev. 4.0

306

Freescale Semiconductor

Operation:

(SP) – $0002

⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP+1))

(SP) – $0002

⇒ SP; YH : YL ⇒ (M(SP) : M(SP+1))

(SP) – $0002

⇒ SP; XH : XL ⇒ (M(SP) : M(SP+1))

(SP) – $0002

⇒ SP; B : A⇒ (M(SP) : M(SP+1))

(SP) – $0001

⇒ SP; CCR ⇒ (M(SP))

Stop CPU Clocks

Description:

Puts the CPU into a wait state. Uses the address of the instruction following

WAI as a return address. Stacks the return address, index registers Y and

X, accumulators B and A, and the CCR, decrementing the SP before each

item is stacked.

The CPU then enters a wait state for an integer number of bus clock cycles.

During the wait state, CPU clocks are stopped, but other MCU clocks can

continue to run. The CPU leaves the wait state when it senses an interrupt

that has not been masked.

Upon leaving the wait state, the CPU sets the appropriate interrupt mask

bit(s), fetches the vector corresponding to the interrupt sensed, and

instruction execution continues at the location the vector points to.

Although the WAI instruction itself does not alter the condition codes, the

interrupt that causes the CPU to resume processing also causes the I mask

bit (and the X mask bit, if the interrupt was XIRQ) to be set as the interrupt

vector is fetched.

WAI

Wait for Interrupt

WAI

CCR Details:

HIN

––––––––

Source Form

Address

Mode

Object Code

Access Detail

HCS12

M68HC12

WAI (before interrupt)

INH

OSSSSsf

OSSSfSsf

WAI (when interrupt comes)

fVfPPP

VfPPP

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