CDCE72010RGCT datasheet(13/73 Pages) TI

13 / 73 page

AC/DC CHARACTERISTICS (CONTINUED)

CDCE72010

www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009

over the specified industrial temperature range of –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

LVPECL Hi Swing Output

fclk

Output frequency

Open loop config.

1500

MHz

LVPECL high-level

VOH

Load, see Figure 5

VCC – 1.11

VCC – 0.87

output voltage

LVPECL low-level output

VOL

Load, see Figure 5

VCC – 2.06

VCC – 1.73

voltage

Differential output

|VOD|

Load, see Figure 5

760

1160

voltage

Reference to output

VCXO at 491.52MHz, Output 1 is divide by 16

phase offset without

and reference at 30.72MHz, M and N delays

tpho

(2)

using available delay

are fixed to one value (set to 0), PFD:

adjustment

240kHz, (M and N = 128)

tpd(LH)/

Propagation delay time,

Crosspoint to crosspoint, load, see Figure 5

3.4

tpd(HL)

VCXO_IN to output

Divide by 1 for all dividers

Divide by 16 for all dividers

tsk(o)

(3)

LVPECL output skew

Divide by 1 for divider 1

2700

Divide by 16 for all other dividers

Output capacitance on

VCC = 3.3 V; VO = 0 V or VCC

Y0 to Y8

Output capacitance on

VCC = 3.3 V; VO = 0 V or VCC

Power-down output

IOPDH

VO = VCC

µA

current

Power-down output

IOPDL

VO = 0V

µA

current

Duty cycle

tr/tf

Rise and fall time

20% to 80% of Voutpp

135

LVDS-TO-LVPECL

Output skew between

tskP_C

LVDS and LVPECL

Crosspoint to VCC/2

0.9

1.1

1.3

outputs

LVCMOS-TO-LVPECL

Output skew between

tskP_C

LVCMOS and LVPECL

Crosspoint to VCC/2

–150

260

700

outputs(4)

(1)

All typical values are at VCC = 3.3 V, TA = 25°C.

(2)

This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and

VCXO delay N).

(3)

The tsk(o) specification is only valid for equal loading of all outputs.

(4)

Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output

signal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS and

LVPECL.

Submit Documentation Feedback

Product Folder Link(s): CDCE72010

CDCE72010RGCT bảng dữ liệu(PDF) 13 Page - Texas Instruments

CDCE72010RGCT bảng dữ liệu(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

bảng dữ liệu tải về

Link URL