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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CDCE72010RGCT bảng dữ liệu(PDF) 39 Page - Texas Instruments |
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CDCE72010RGCT bảng dữ liệu(HTML) 39 Page - Texas Instruments |
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39 / 73 page  CDCE72010 www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009 Register 3: CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION 0 A0 Address 0 1 1 A1 Address 1 1 2 A2 Address 2 0 3 A3 Address 3 0 When set to 0, the REF-clock frequency detector is ON 4 0 DIS_FDET_REF PLL Freq. Detect EEPROM When set to 1, it is switched OFF When set to 1, the feedback path frequency detector is switched OFF 5 1 DIS_FDET_FB Diagnostics EEPROM (TI Test-GTME) 6 2 BIAS_DIV01<0> When BIAS_DIV01<1:0> = EEPROM Output Divider 00, No current reduction for all output-divider 0 and 1 01, Current reduction for all output-divider by about 20% 7 3 BIAS_DIV01<1> EEPROM 10, Current reduction for all output-divider by about 30% 8 4 BIAS_DIV23<0> When BIAS_DIV23<1:0> = EEPROM Output Divider 00, No current reduction for all output-divider 2 and 3 01, Current reduction for all output-divider by about 20% 9 5 BIAS_DIV23<1> EEPROM 10, Current reduction for all output-divider by about 30% 10 6 PH3ADJC0 11 7 PH3ADJC1 12 8 PH3ADJC2 13 9 PH3ADJC3 Output 3 Coarse phase adjust select for output divider 3 EEPROM 14 10 PH3ADJC4 15 11 PH3ADJC5 16 12 PH3ADJC6 17 13 OUT3DIVRSEL0 18 14 OUT3DIVRSEL1 19 15 OUT3DIVRSEL2 OUTPUT DIVIDER 3 Ratio Select 20 16 OUT3DIVRSEL3 Output 3 EEPROM (See Table 7) 21 17 OUT3DIVRSEL4 22 18 OUT3DIVRSEL5 23 19 OUT3DIVRSEL6 When set to 0, the divider is disabled 24 20 EN3DIV Output 3 EEPROM When set to 1, the divider is enabled 25 21 PECL3HISWING Output 3 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM CD1 PIN is high and DIVPHA3CD1H is set to low Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 3 26 22 DIVPHA3CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA3CD1H is set to high Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 3 CD1 PIN is Low and DIVPHA3CD1L is set to low Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 3 27 23 DIVPHA3CD1L CD1 Low EEPROM CD1 PIN is Low and DIVPHA3CD1L is set to high Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 3 28 24 OUTBUF3CD2LX Output Buffer 3 Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) = 01:LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 29 25 OUTBUF3CD2LY 30 26 OUTBUF3CD2HX Output Buffer 3 Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 31 27 OUTBUF3CD2HY Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Link(s): CDCE72010 |
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