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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CDCE72010RGCT bảng dữ liệu(PDF) 37 Page - Texas Instruments |
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CDCE72010RGCT bảng dữ liệu(HTML) 37 Page - Texas Instruments |
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37 / 73 page  CDCE72010 www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009 Register 1: CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION 0 A0 Address 0 1 1 A1 Address 1 0 2 A2 Address 2 0 3 A3 Address 3 0 4 0 ACDCSEL Input Buffers If Set to 0 AC Termination, If set to 1 DC termination EEPROM 5 1 HYSTEN Input Buffers If Set to 1 Input Buffers Hysteresis enabled EEPROM 6 2 TERMSEL Input Buffers If Set to 0 Input Buffer Internal Termination enabled EEPROM 7 3 PRIINVBB Input Buffers If Set to 1 Primary Input Negative Pin biased with internal VBB voltage. EEPROM 8 4 SECINVBB Input Buffers If Set to 1 Secondary Input Negative Pin biased with internal VBB voltage EEPROM 9 5 FAILSAFE Input Buffers If Set to 1 Fail Safe is enabled for all input buffers. EEPROM 10 6 PH1ADJC0 11 7 PH1ADJC1 12 8 PH1ADJC2 13 9 PH1ADJC3 Output 0 and 1 Coarse phase adjust select for output divider 1 EEPROM 14 10 PH1ADJC4 15 11 PH1ADJC5 16 12 PH1ADJC6 17 13 OUT1DIVRSEL0 18 14 OUT1DIVRSEL1 19 15 OUT1DIVRSEL2 OUTPUT DIVIDER 1 Ratio Select 20 16 OUT1DIVRSEL3 Output 0 and 1 EEPROM (See Table 7) 21 17 OUT1DIVRSEL4 22 18 OUT1DIVRSEL5 23 19 OUT1DIVRSEL6 When set to 0, the divider is disabled 24 20 EN01DIV Output 0 and 1 EEPROM When set to 1, the divider is enabled 25 21 PECL1HISWING Output 1 High output voltage swing in LVPECL Mode if set to 1 EEPROM CD1 PIN is high and DIVPHA1CD1H is set to low Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 1 26 22 DIVPHA1CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA1CD1H is set to high Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 1 CD1 PIN is low and DIVPHA1CD1L is set to low Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 1 27 23 DIVPHA1CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA1CD1L is set to high Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 1 28 24 OUTBUF1CD2LX EEPROM Output Buffer 1 Signaling Selection when CD2 in low CD2 Low (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 29 25 OUTBUF1CD2LY 30 26 OUTBUF1CD2HX EEPROM Output Buffer 1 Signaling Selection when CD2 in high CD2 High (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 31 27 OUTBUF1CD2HY Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 37 Product Folder Link(s): CDCE72010 |
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