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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CDCE72010RGCT bảng dữ liệu(PDF) 40 Page - Texas Instruments |
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CDCE72010RGCT bảng dữ liệu(HTML) 40 Page - Texas Instruments |
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40 / 73 page  CDCE72010 SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com Register 4: CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION 0 A0 Address 0 0 1 A1 Address 1 0 2 A2 Address 2 1 3 A3 Address 3 0 4 0 RESERVED EEPROM 5 1 RESERVED EEPROM 6 2 RESERVED EEPROM 7 3 RESERVED EEPROM If set to 1 it will 3-state the charge pump to act as a HOLD on Loss of Reference 8 4 HOLDONLOR HOLD- Over EEPROM Clocks ( Primary and Secondary) 9 5 RESERVED EEPROM 10 6 PH4ADJC0 11 7 PH4ADJC1 12 8 PH4ADJC2 13 9 PH4ADJC3 Output 4 Coarse phase adjust select for output divider 4 EEPROM 14 10 PH4ADJC4 15 11 PH4ADJC5 16 12 PH4ADJC6 17 13 OUT4DIVRSEL0 18 14 OUT4DIVRSEL1 19 15 OUT4DIVRSEL2 OUTPUT DIVIDER 4 Ratio Select 20 16 OUT4DIVRSEL3 Output 4 EEPROM (See Table 7) 21 17 OUT4DIVRSEL4 22 18 OUT4DIVRSEL5 23 19 OUT4DIVRSEL6 When set to 0, the divider is disabled 24 20 EN4DIV Output 4 EEPROM When set to 1, the divider is enabled 25 21 PECL4HISWING Output 4 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM CD1 PIN is high and DIVPHA4CD1H is set to low Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 4 26 22 DIVPHA4CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA4CD1H is set to high Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 4 CD1 PIN is low and DIVPHA4CD1L is set to low Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 4 27 23 DIVPHA4CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA4CD1L is set to high Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 4 28 24 OUTBUF4CD2LX Output Buffer 4 Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 29 25 OUTBUF4CD2LY 30 26 OUTBUF4CD2HX Output Buffer 4 Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 31 27 OUTBUF4CD2HY 40 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010 |
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