CDCE72010RGCT datasheet(65/73 Pages) TI

65 / 73 page

POWER UP RESET, POWER DOWN MODE AND RESET OR HOLD

POR

PDor

Sleep

Reset

Hold

ResetSPIInterfaceandRegister12toDefault

Power AllClockingCircuitryDown

-ShutDown All AnalogCircuitry(/PD=0orSleep=0)

-ShutDown AllDigitalCircuitry(/PD=0orSleep=0)

-Disable AllOutputBuffers(/PD=0orSleep=0)

-LoadEEPROMIntoRAMWhenReleased(atRisingEdgeof/PD)

ResetDigitalCircuitry

-Disable AllOutputBuffers(When/RESET=0)

-ResetPLL (LoadWithRAMContentValuesatRisingEdge)

-ResetOutputDividersandPhase AdjustCircuitry(atRisingEdge)

WhenHoldFunctionIs Asserted

-Tri-statetheChargePumpOutputWhen/HOLD=0

HoldFunctionIsDeassertedWhen

-/HOLD=1andWeHaveValidReferenceClock

Reset

Hold

/PD

/Reset_Hold

REG12:

REG11:

REG4:

(ForceSleep/PDand/RESETor/HOLD)

LossofReference

Sleep

CDCE72010

www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009

The CDCE72010 is designed to address various clock synchronization applications. Some functions can be set

to be in automatic and manual mode or some functions can be controlled by software or by the internal circuitry.

Figure 31 below explains the various functionalities of power up reset internal circuitry functionality, power down

functionality and reset functionality. The hold function shares the same block with Reset and one bit in the

EEPROM will select either function.

Figure 31. Powerup, Reset, and Powerdown Block Diagram

Submit Documentation Feedback

Product Folder Link(s): CDCE72010

CDCE72010RGCT bảng dữ liệu(PDF) 65 Page - Texas Instruments

CDCE72010RGCT bảng dữ liệu(HTML) 65 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

bảng dữ liệu tải về

Link URL