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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CDCE72010RGCT bảng dữ liệu(PDF) 38 Page - Texas Instruments |
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CDCE72010RGCT bảng dữ liệu(HTML) 38 Page - Texas Instruments |
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38 / 73 page  CDCE72010 SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com Register 2: CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION 0 A0 Address 0 0 1 A1 Address 1 1 2 A2 Address 2 0 3 A3 Address 3 0 4 0 DLYM0 Reference Phase Delay M Bit0 5 1 DLYM1 DELAY M Reference Phase Delay M Bit1 EEPROM 6 2 DLYM2 Reference Phase Delay M Bit2 7 3 DLYN0 Feedback Phase Delay N Bit0 8 4 DLYN1 DELAY N Feedback Phase Delay N Bit1 EEPROM 9 5 DLYN2 Feedback Phase Delay N Bit2 10 6 PH2ADJC0 11 7 PH2ADJC1 12 8 PH2ADJC2 13 9 PH2ADJC3 Output 2 Coarse phase adjust select for output divider 2 EEPROM 14 10 PH2ADJC4 15 11 PH2ADJC5 16 12 PH2ADJC6 17 13 OUT2DIVRSEL0 18 14 OUT2DIVRSEL1 19 15 OUT2DIVRSEL2 OUTPUT DIVIDER 2 Ratio Select 20 16 OUT2DIVRSEL3 Output 2 EEPROM (See Table 7) 21 17 OUT2DIVRSEL4 22 18 OUT2DIVRSEL5 23 19 OUT2DIVRSEL6 When set to 0, the divider is disabled 24 20 EN2DIV Output 2 EEPROM When set to 1, the divider is enabled 25 21 PECL2HISWING Output 2 High output voltage swing in LVPECL Mode if set to 1 EEPROM CD1 PIN is high and DIVPHA2CD1H is set to low Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 2 26 22 DIVPHA2CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA2CD1H is set to high Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 2 CD1 PIN is low and DIVPHA2CD1L is set to low Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 2 27 23 DIVPHA2CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA2CD1L is set to high Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 2 28 24 OUTBUF2CD2LX Output Buffer 2 Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 29 25 OUTBUF2CD2LY 30 26 OUTBUF2CD2HX Output Buffer 2 Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 31 27 OUTBUF2CD2HY 38 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010 |
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