CDCE72010RGCT datasheet(52/73 Pages) TI

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PHASE DELAY FOR M AND N

Delay Block in M/N Path

CDCE72010

SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com

Table 11. Reference Delay M (PRI_REF or SEC_REF) and Feedback Delay N (VCXO) Phase Adjustment

(Register 2 RAM Bits [5:0]) (1)

DLYM2/DLYN2

DLYM1/DLYN1

DLYM0/DLYN0

PHASE OFFSET

0ps(2)

±160ps

±320ps

±480ps

±830ps

±1130ps

±1450ps

±1750ps

(1)

If Progr Delay M is set, all Yx outputs are lagging to the Reference Clock according to the value set. If Progr Delay N is set, all Yx

outputs are leading to the Reference Clock according to the value set. Above are typical values at VCC = 3.3 V, TA = 25°C, PECL-output

relate to Div4 mode.

(2)

Default

Table 12. Reference Divider M/N 14-Bit (Register 10 RAM Bits [13:0] for M and RAM Bits [27:14] for N)

N13

N12

N11

N10

DIV BY(1)

•

128(2)

•

16382

16383

16384

(1)

If the divider value is Q, then the code will be the binary value of (Q - 1).

(2)

Default

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