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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CDCE72010RGCT bảng dữ liệu(PDF) 42 Page - Texas Instruments |
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CDCE72010RGCT bảng dữ liệu(HTML) 42 Page - Texas Instruments |
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42 / 73 page  CDCE72010 SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com Register 6: CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION 0 A0 Address 0 0 1 A1 Address 1 1 2 A2 Address 2 1 3 A3 Address 3 0 0 Feedback Frequency Detector is connected to the Lock Detector 4 0 FB_FD_DESEL 1 Feedback Frequency Detector is disconnected from the Lock Detector LOCK-DET EEPROM 5 1 RESERVED Set to “0” 0 FB-Deterministic Clock divided by 1 6 2 FBDETERM_DIV_SEL 1 FB- Deterministic Clock divided by 2 FB-Divider / 0 FB-Deterministic-DIV2-Block in normal operation 7 3 FBDETERM_DIV2_DIS Deterministic EEPROM 1 FB-Deterministic-DIV2 reset (here REG6_RB<2> == “0”) Blocks 0 FB-Divider started with delay block (RC), normal operation 8 4 FB_START_BYPASS 1 FB-Divider can be started with external REF_SEL-signal (pin) All Output 0 Output-Dividers started with delay block (RC), normal operation 9 5 DET_START_BYPASS EEPROM Dividers 1 Output-Dividers can be started with external NRESET-signal (pin) 10 6 PH6ADJC0 11 7 PH6ADJC1 12 8 PH6ADJC2 13 9 PH6ADJC3 Output 6 Coarse phase adjust select for output divider 6 EEPROM 14 10 PH6ADJC4 15 11 PH6ADJC5 16 12 PH6ADJC6 17 13 OUT6DIVRSEL0 18 14 OUT6DIVRSEL1 19 15 OUT6DIVRSEL2 OUTPUT DIVIDER 6 Ratio Select 20 16 OUT6DIVRSEL3 Output 6 EEPROM (See Table 7) 21 17 OUT6DIVRSEL4 22 18 OUT6DIVRSEL5 23 19 OUT6DIVRSEL6 When set to 0, the divider is disabled 24 20 EN6DIV Output 6 EEPROM When set to 1, the divider is enabled 25 21 PECL6HISWING Output 6 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM CD1 PIN is high and DIVPHA6CD1H is set to low Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 6 26 22 DIVPHA6CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA6CD1H is set to high Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 6 CD1 PIN is low and DIVPHA6CD1L is set to low Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 6 27 23 DIVPHA6CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA6CD1L is set to high Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 6 28 24 OUTBUF6CD2LX Output Buffer 6 Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 29 25 OUTBUF6CD2LY 30 26 OUTBUF6CD2HX Output Buffer 6 Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 31 27 OUTBUF6CD2HY 42 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010 |
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