AT697F datasheet(55/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

Error reporting

Fatal (abort) and

address parity errors

On a fatal error ( or address parity error ), the interface flushes all the current buffer requests and

all other buffer requests. Then, the interface reports the fatal error driven logical one the

PCIITE CMFER.

The PCI core is restarted as soon as a new request is engaged.

DMA transfer

A DMA facility is available on the AT697 processor. The DMA transfer are performed through the

PCI interface. The DMA controller executes data transfer between the local memory and a

remote target on the PCI bus.

The processor core only intervenes for the initiation of the transfer. Once transfer is initiated,

DMA controller is fully autonomous. DMA transfers take place in background of the processor

core activity. Thus, interrupts are provided to help to synchronise the application with start and

end of the transfer.

The DMA interface executes only word-size transactions with all 4 byte lanes enabled.

Operation

The DMA is enabled setting logical one the PCIIC MOD. To synchronize the application with

the start and the end of the transaction, two interrupts can be enabled : PCIITE DMAER for

transfer control and PCIITE IMIER for error control.

Each DMA sequence shall program the following parameters :

•

PCI start address

•

PCI command type

•

number of words to be transferred

•

the start address in the local memory

A DMA transfer is performed assuming the following operations are done in the given order :

Write the PCI start address of burst to the PCI start address register (PCISA). The PCISA

identical to the address of the previous DMA request.

Write together the PCI command and the number of words to be transfered in the PCI

DMA configuration register (PCIDMA).

Writing to the PCIDMA passes the PCI address, the word count and the PCI command to

the PCI core and initiates the transaction on the PCI bus.

Write the start address in the local memory map to the PCI DMA address register

(PCIDMAA).

Once the three operation are executed, data transfer is started in background. Once the speci-

fied number of words is transfered, the interface set logical one the PCIITE

DMAER and

generate an interrupt if enabled. Then DMA controller goes back to idle state.

Error Reporting

If the PCI core does not accept the DMA cycle request, the DMA state controller remains locked

and an error is reported as initiator error with the PCIITE

IMIER bit set logical one. If the

request on the PCI core was just delayed, rewriting PCIDMAA may succeed. If the problem per-

sists, reset the interface by writing –1 (0xFFFFFFFF) to PCIIC.

Transfer Limitation

DMA transaction may never cross a 1 KByte border. The value represented by PCIDMAA(9:2)

+ PCIDMA(7:0) must be less than 256. If this restriction is not respected, the data transfer stops

at the 1 kByte border. Then the PCI core is flushed. Simultaneously, in the PCI interrupt pending

are asserted logical one.

If enabled with the PCI interrupr enable register (PCIITE) and unmasked in the general interrupt

mask register, the PCI interrupt 14 is generated (TT = 0x1E).

Debug Facilities

Not implemented for application use.

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