AT697F datasheet(93/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

Caches Register

Table 57. Cache Control Register - CCR

Address = 0x80000014

reserved

r/w r/w r/w

r/w

r/w r/w

r/w

11110111

Bit Number

Mnemonic

Description

Data cache snoop enable

If set, will enable data cache snooping.

Flush data cache

If set, will flush the data cache. Always reads as zero.

Flush Instruction cache

If set, will flush the instruction cache. Always reads as zero.

20..19

cpc[1:0]

Cache parity bits

Indicates how many parity bits are used to protect the caches

“00” = none,

“01” = 1 parity bits,

“10” = 2 parity bits,

“11” = not used

18..17

cpte[1:0]

Cache parity test bits

These bits are XOR’ed to the data and tag parity bits during diagnostic writes.

Instruction burst fetch

This bit enables burst fill during instruction fetch.

Instruction cache flush pending

This bit is set when an instruction cache flush operation is in progress.

Data cache flush pending

This bit is set when an data cache flush operation is in progress.

13..12

ite[1:0]

Instruction cache tag error counter

This filed is incremented every time an instruction cache tag parity error is detected.

11.10

ide[1:0]

Instruction cache data error counter

This field is incremented each time an instruction cache data sub-block parity error is detected.

9..8

dte[1:0]

Data cache tag error counter

This filed is incremented every time a data cache tag parity error is detected.

7..6

dde[1:0]

Data cache data error counter

This field is incremented each time an instruction cache data sub-block parity error is detected

Data Cache Freeze on Interrupt

If set, the data cache will automatically be frozen when an asynchronous interrupt is taken.

Instruction Cache Freeze on Interrupt

If set, the instruction cache will automatically be frozen when an asynchronous interrupt is taken.

3..2

dcs[1:0]

Data Cache state

Define the current data cache according to the following :

“X0” = disabled

“01” = frozen

“11” = enabled

Set to “00” at reset.

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