AT697F datasheet(92/155 Pages) ATMEL

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Table 55. Fail Address Register - FAILAR

Address = 0x8000000C

fa[31:0]

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Bit Number

Mnemonic

Description

31..0

fa[31:0]

Failing Address

This field contains the address of the access that triggered an error response. This register is updated each

time an error occurs on the internal bus.

Table 56. Fail Status Register - FAILSR

Address = 0x80000010

reserved

hmaster[3:0]

hsize[2:0]

r/w

r/w r/w

xxxxxxxxxxxxxxx

Bit Number

Mnemonic

Description

EDAC Correctable error

Set when a correctable EDAC error is detected.

Error Valid.

Set when a new error occurred.

Read/Write.

This bit is set if the failed access was a read cycle, otherwise it is cleared.

6..3

hmaster[3:0]

AHB master.

This field contains the HMASTER[3:0] of the failed access.

2..0

hsize[2:0]

Transfer Size.

This filed contains the HSIZE[2:0] of the failed transfer.

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

Note:

Any access triggering an error response on the AHB bus will be registered in two registers; AHB

failing address register and AHB status register.The failing address register will store the address

of the access while the AHB status register will store the access and error type.The registers are

updated when an error occur, and the EV (error valid) is not set. When the EV bit is set, interrupt 1

is generated to inform the processor about the error. After an error, the EV bit has to be reset by

software.

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