AT697F datasheet(73/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

System Clock

Overview

The AT697F clock system is mainly based on two main clock trees: the PCI clock and the CPU

clock. The following figure presents the clock system of the processor and its distribution.

Figure 47.

PLL

Alternate

PCI clock

CLK

BYPASS

PDIV4

LOCK

UART clock

Uart Control Reg.

UACn

PCI Core

SDCLK

CPU Core

GPI

Timers

Uarts

Memory

Control

PCI

Wrapper

Interrupt

Controller

Caches

Reg. File

Clock Distribution

PCI Clock

The PCI clock is dedicated to the PCI Interface. It is used in particular by the PCI wrapper that

shares its activity between the two clock domains.

External Clock

The PCI interface and its associated wrapper can only be driven from an external clock. The PCI

clock shall be connected to the PCI_CLK pin of the PCI interface. This input shall be driven at a

frequency in the range of 0 up to 33MHz.

CPU Clock

The CPU clock is routed to the parts of the system concerned with operation of the SPARC core.

Examples of such modules are the CPU core itself, the register files... The CPU clock is also

used by the majority of the I/O modules like Timers, Memory controller, Interrupt Controller, with

the exception of the PCI Interface.

The CPU clock is driven either directly by an external oscillator or by the internal PLL.

External Clock

To drive the device directly from an external clock source, the CLK input shall be driven by an

external clock generator while the BYPASS pin is driven high. In that way, the CPU clock is the

direct representation of the clock applied to CLK.

When the external CPU clock source is selected, the clock input can be driven at a frequency in

the range of 0MHz up to 100MHz.

PLL

Overview

The CPU clock can be issued from the internal PLL. This PLL contains a phase/frequency

detector, charge pump, voltage control oscillator, low pass filter, lock detector and divider.

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