AT697F datasheet(86/155 Pages) ATMEL

86 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

Note:

The prom bank size is coded in the same way as the ram bank size in MCFG2. The prom bank

size is used when an 8-bit prom is used with EDAC enabled - the last 25% of the prom bank is

used to store the EDAC checksums and cannot be used to store instructions or data.

During power-up, the prom width (bits [9:8]) are set with value on PIO[1:0] inputs. The prom

waitstates fields are set to 15 (maximum) and prom bank size is set to “0000”. External bus error

and bus ready are disabled. All other fields are undefined.

Table 46. Memory Configuration Register 2 - MCFG2

Address = 0x80000004

reserved

r/w r/w

r/w

r/w r/w

r/w

r/w r/w r/w

r/w

111

000

xxxx

Bit Number

Mnemonic

Description

sdrref

SDRAM refresh.

If set, the SDRAM refresh will be enabled.

trp

SDRAM t

RP timing.

tRP will be equal to 2 or 3 system clocks (0/1).

29..27

trfc[2:0]

SDRAM t

RFC timing.

tRF will be equal to 3 + field-value system clocks.

sdrcas

SDRAM CAS delay.

Selects 2 or 3 cycle CAS delay (0/1). When changed, a LOAD-COMMAND-REGISTER command must be

issued at the same time. Also sets RAS/CAS delay (tRCD).

25..23

sdrbs[2:0]

SDRAM banks size.

Defines the banks size for SDRAM chip selects:

“000” = 4 Mbyte,

“001” = 8 Mbyte,

“010” = 16 Mbyte,

...,

“111”=512 Mbyte.

22..21

sdrcls[1:0]

SDRAM column size.

“00” = 256 when sdrbs = “111”,

“01” = 512 when sdrbs = “111”,

“10” = 1024 when sdrbs = “111”,

“11” = 4096 when sdrbs = “111”,

= 2048 otherwise.

20..19

sdrcmd[1:0]

SDRAM command.

Writing a non-zero value will generate an SDRAM command:

“01” = PRECHARGE,

“10” = AUTO-REFRESH,

“11” = LOAD-COMMAND-REGISTER.

The field is reset after command has been executed.

SDRAM enable.

If set, the SDRAM controller will be enabled.

SRAM disable.

If set together with bit 14 (SDRAM enable), the static ram access will be disabled.

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