AT697F datasheet(72/155 Pages) ATMEL

72 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

Execution Mode

Reset Mode

When the RESET input is asserted for at least two cycles, the processor enters reset mode.

Under this mode, the CPU and all the peripherals are halted. Only the following registers are

affected by the reset. All other registers maintain their value or are undefined.

Table 26.

Description

Reset Value

program counter

0x0000 0000

nPC

new program counter

0x0000 0004

PSR

processor status register

et = 0

s = 1

CCR

cache control register

0x0000 0000

MCFG1 PRWDH

PROM bus width

PIO[1:0]

MCFG3 PE

PROM EDAC enable

PIO[2]

Reset Operation

When RESET is deasserted, execution restarts from address 0.

Debug Mode

Debug mode can be entered when the DSU is enabled through the external DSUEN pin. This

allows read/write access to all processor registers and caches memories. In debug mode, the

processor pipeline is held and the processor is controlled by the DSU.

Power-down/Idle

Mode

AT697 can be idled by writing any value to the power-down register. During power-down mode,

only the integer unit is halted. All other functions and peripherals operate as nominal.

When a single write to the idle register is performed, idle mode is entered on the next load

instruction. Idle mode is terminated when an unmasked interrupt with higher level than the cur-

rent processor interrupt level is pending. Then, the integer unit is re-enabled.

Here is a simple example allowing Idle mode entry :

! write any value to Idle register

st %g2,[%g1 + 0x18]

! enter Idle mode

ld [%o1 + 0x08],%g3

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