AT697F datasheet(78/155 Pages) ATMEL

78 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

Registers

Description

Table 29. Register legend

Address = 0x01010101

Bit Number

...

field name

field

reserved

bit

access type

r=read access

w=write acces

r/w=read and write access

default value after reset

100

x = undefined or non affected by reset

Integer Unit

Registers

Table 30. Processor State Register- PSR

impl[3:0]

ver[3:0]

reserved

pil[3:0]

cwp[4:0]

r/w

0001

xxxxxx

xxxx

00000

Bit Number

Mnemonic

Description

31..28

impl[3:0]

Implementation or class of implementations of the architecture.

27..24

ver[3:0]

Identify one or more particular implementations or is a readable and writable state field whose properties are

implementation-dependent.

indicates whether the ALU result was negative for the last instruction modifying icc field.

1 = negative

0 = not negative.

indicates whether the ALU result was zero for the last instruction modifying icc field.

1 = zero

0 = not zero.

indicates whether the ALU result was within the range of (was representable in) 32-bit 2’s complement notation

for the last instruction that modified the icc field. 1 = overflow, 0 = no overflow.

indicates whether a 2’s complement carry out (or borrow) occurred for the last instruction that modified the icc

field. Carry is set on addition if there is a carry out of bit 31. Carry is set on subtraction if there is borrow into bit

31. 1 = carry, 0 = no carry.

determines whether the implementation-dependent oprocessor is enabled. If disabled, a coprocessor

instruction will trap. 1 = enabled, 0 = disabled. If an

implementation does not support a coprocessor in ardware, PSR.EC should always read as 0 and writes to it

should be ignored.

determines whether the FPU is enabled. If disabled, a floating-point instruction will trap. 1 = enabled, 0 =

disabled. If an implementation does not support a hardware FPU, PSR.EF should always read as 0 and writes

to it should be ignored.

11..8

pil[3:0]

identify the interrupt level above which the processor will accept an interrupt.

determines whether the processor is in supervisor or user mode. 1 = supervisor mode, 0 = user mode.

contains the value of the S bit at the time of the most recent trap.

determines whether traps are enabled. A trap automatically resets ET to 0. When ET=0, an interrupt request is

ignored and an exception trap causes the IU to halt execution, which typically results in a reset trap that

resumes execution at address 0. 1 = traps enabled, 0 = traps disabled.

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