TL28L92 datasheet(31/61 Pages) TI

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3.3.1.4 Mode Register 0 Channel B (MR0B)

3.3.1.5 Mode Register 1 Channel B (MR1B)

3.3.1.6 Mode Register 2 Channel B (MR2B)

3.3.2

Clock Select Registers

3.3.2.1 Clock Select Register Channel A (CSRA)

TL28L92

3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

www.ti.com

SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008

MR0B (address 0x8) is accessed when the channel B MR pointer points to MR1. The pointer is set to

MR0 by RESET or by a set pointer command applied via CRB. After reading or writing MR0B, the pointer

will point to MR1B.

The bit definitions for this register are identical to MR0A, except the FIFO size bit and that all control

actions apply to the channel B receiver, transmitter, the corresponding inputs and outputs. MR0B[2:0] are

reserved.

MR1B (address 0x8) is accessed when the channel B MR pointer points to MR1. The pointer is set to

MR1 by RESET or by a set pointer command applied via CRB. After reading or writing MR1B, the pointer

will point to MR2B.

The bit definitions for this register are identical to MR1A, except that all control actions apply to the

channel B receiver and transmitter and the corresponding inputs and outputs.

MR2B (address 0x8) is accessed when the channel B MR pointer points to MR2, which occurs after any

access to MR1B. Accesses to MR2B do not change the pointer.

The bit definitions for mode register are identical to the bit definitions for MR2A, except that all control

actions apply to the channel B receiver and transmitter and the corresponding inputs and outputs.

Table 3-30. Clock Select Register Channel A (CSRA) (Address 0x1) and

Clock Select Register Channel B (CSRB) (Address 0x9) Bit Allocation

receiver clock select code

transmitter clock select code

Table 3-31. Clock Select Register Channel A (CSRA) (Address 0x1) Bit Description

BIT(S)

SYMBOL

DESCRIPTION

7 to 4

–

Receiver clock select. The baud rate clock for the channel A receiver is as shown in Table 3-32, except as

follows:

1110 = IP4 – 16

1111 = IP4 – 1

The receiver clock is always a 16

× clock except for CSRA[7:4] = 1111

3 to 0

–

Transmitter clock select. The baud rate clock for the channel A transmitter is as shown in Table 3-32, except

as follows:

1110 = IP3 – 16

1111 = IP3 – 1

The transmitter clock is always a 16

× clock except for CSRA[3:0] = 1111

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