TL28L92 datasheet(29/61 Pages) TI

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TL28L92

3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

www.ti.com

SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008

Table 3-27. Mode Register 2 Channel A (MR2A) (Address 0x0) Bit Description

BIT(S)

SYMBOL

DESCRIPTION

7 and 6

–

Channel A mode select. Each channel of the DUART can operate in one of the following four modes:

00 = Normal mode (default)

01 = Automatic echo mode

10 = Local loopback mode

11 = Remote loopback mode

Table 3-28 gives a description of the channel modes.

The user must exercise care when switching into and out of the various modes. The selected mode will be

activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted

character. Likewise, if a mode is deselected the device will switch out of the mode immediately. An

exception to this is switching out of auto echo or remote loopback modes: if the deselection occurs just after

the receiver has sampled the stop bit (indicated in auto echo by assertion of RxRDY), and the transmitter is

enabled, the transmitter will remain in auto echo mode until the entire stop has been retransmitted.

–

Channel A transmitter request to send (RTS) control.

0 = No RTS control

1 = RTS control

This bit controls the deactivation of the RTSAN output (OP0) by the transmitter. This output is normally

asserted by setting OPR[0] and negated by resetting OPR[0]. MR2A[5] = 1 caused OPR[0] to be reset

automatically one bit time after the characters in the channel A transmit shift register and in the Tx FIFO, if

any, are completely transmitted including the programmed number of stop bits, if the transmitter is not

enabled.

This feature can be used to automatically terminate the transmission of a message as follows (line

turnaround):

Program auto-reset mode: MR2A[5] = 1

Enable transmitter

Assert RTSAN: OPR[0] = 1

Send message

Disable transmitter after the last character is loaded into the channel A Tx FIFO

The last character will be transmitted and OPR[0] will be reset one bit time after the last stop bit, causing

RTSAN to be negated

–

Channel A transmitter clear to send (CTS) control.

0 = Input CTSAN(IP0) has no effect on the transmitter

1 = CTS control enabled

If this bit is a 1, the transmitter checks the state of CTSAN (IP0) each time it is ready to send a character. If

IP0 is asserted (LOW), the character is transmitted. If it is negated (HIGH), the TxDA output remains in the

marking state and the transmission is delayed until CTSAN goes LOW. Changes in CTSAN while a

character is being transmitted do not affect the transmission of that character.

3 to 0

–

Stop bit length select. This field programs the length of the stop bit appended to the transmitted character.

Stop bit lengths of 9/16 to 1 and 1 –

16 to 2 bits, in increments of

16 bit, can be programmed for character

lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1 – 1/16 to 2 stop bits can be programmed in

increments of 1/16 bit. In all cases, the receiver only checks for a mark condition at the center of the stop bit

position (one half-bit time after the last data bit, or after the parity bit if enabled is sampled). Refer to

Table 3-29 for the values.

If an external 1

× clock is used for the transmitter:

MR2A[3] = 0 selects one stop bit

MR2A[3] = 1 selects two stop bits

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