TL28L92 datasheet(15/61 Pages) TI

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Functional Description

2.1

Block Diagram

2.1.1

Data Bus Buffer

2.1.2

Operation Control

2.1.3

Interrupt Control

2.1.4

FIFO Configuration

2.1.5

68xxx Mode

TL28L92

3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

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SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008

The TL28L92 DUART consists of the following eight major sections: data bus buffer, operation control,

interrupt control, timing, communications channels A and B, input port and output port. See Figure 1-1 and

Figure 1-2.

The data bus buffer provides the interface between the external and internal data buses. It is controlled by

the operation control block to allow read and write operations to take place between the controlling CPU

and the DUART.

The operation control logic receives operation commands from the CPU and generates appropriate

signals to internal sections to control device operation. It contains address decoding and read and write

circuits to permit communications with the microprocessor via the data bus.

A single active LOW interrupt output (INTRN) is provided which is activated upon the occurrence of any of

eight internal events. Associated with the interrupt system are the Interrupt Mask Register (IMR) and the

Interrupt Status Register (ISR). The IMR can be programmed to select only certain conditions to cause

INTRN to be asserted. The ISR can be read by the CPU to determine all currently active interrupting

conditions. Outputs OP3 to OP7 can be programmed to provide discrete interrupt outputs for the

transmitter, receivers, and counter/timer. When OP3 to OP7 are programmed as interrupts, their output

buffers are changed to the open-drain active LOW configuration. The OP pins may be used for DMA and

modem control as well (see Section 3.4).

Each receiver and transmitter has a 16 byte FIFO. These FIFOs may be configured to operate at a fill

capacity of either 8 bytes or 16 bytes. This feature may be used if it is desired to operate the TL28L92 in

strict compliance with the SC26C92. The 8 byte or 16 byte mode is controlled by the MR0A[3] bit. A logic

0 value for this bit sets the 8-bit mode (the default); a logic 1 sets the 16 byte mode. MR0A bit 3 sets the

FIFO size for both channels.

The FIFO fill interrupt level automatically follow the programming of the MR0A[3] bit. See Table 3-22 and

Table 3-23.

When the I/M pin is connected to GND (ground), the operation of the TL28L92 switches to the bus

interface compatible with the Motorola bus interfaces. Several of the pins change their function as follows:

• IP6 becomes IACKN input

• RDN becomes DACKN

• WRN becomes R/WN

The interrupt vector is enabled and the interrupt vector will be placed on the data bus when IACKN is

asserted LOW. The interrupt vector register is located at address 0xC. The contents of this register are set

to 0x0F on the application of RESETN.

The generation of DACKN uses two positive edges of the X1 clock as the DACKN delay from the falling

edge of CEN. If the CEN is withdrawn before two edges of the X1 clock occur, the generation of DACKN

is terminated. Systems not strictly requiring DACKN may use the 68xxx mode with the bus timing of the

80xxx mode greatly decreasing the bus cycle time.

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Functional Description

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