TL28L92 datasheet(43/61 Pages) TI

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3.3.14 Counter/Timer Registers

counter/timerclockfrequency

2×16×(desiredbaudrate)

TL28L92

3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

www.ti.com

SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008

Table 3-59. Counter/Timer Preset Upper (CTPU) (Address 0x6) Bit Description

BIT(S)

SYMBOL

DESCRIPTION

7:0

–

The upper eight (8) bits for the 16-bit counter/timer preset register

Table 3-60. Counter/Timer Preset Lower (CTPL) (Address 0x7) Bit Description

BIT(S)

SYMBOL

DESCRIPTION

7:0

–

The lower eight (8) bits for the 16-bit counter/timer preset register

The CTPU and CTPL hold the eight MSBs and eight LSBs, respectively, of the value to be used by the

counter/timer in either the counter or timer modes of operation. The minimum value which may be loaded

into the CTPU/CTPL registers is 0x0002. Note that these registers are write only and cannot be read by

the CPU.

In the timer mode, the C/T generates a square wave whose period is twice the value (in C/T clock periods)

of the CTPU and CTPL. The waveform so generated is often used for a data clock. The formula for

calculating the divisor n to load to the CTPU and CTPL for a particular 1

× data clock is:

Often this division will result in a non-integer number; 26.3, for example. One can only program integer

numbers in a digital divider. Therefore, 26 would be chosen. This gives a baud rate error of 0.3/26.3 which

is 1.14 %; well within the ability asynchronous mode of operation.

The C/T will not be running until it receives an initial start counter command (read at address A3 to A0 =

1110). After this, while in timer mode, the C/T will run continuously. Receipt of a start counter command

(read with A3 to A0 = 1110) causes the counter to terminate the current timing cycle and to begin a new

cycle using the values in CTPU and CTPL. If the value in CTPU and CTPL is changed, the current

half-period will not be affected, but subsequent half periods will be affected.

The counter ready status bit (ISR[3]) is set once each cycle of the square wave. The bit is reset by a stop

counter command (read with A3 to A0 = 1111). The command however, does not stop the C/T. The

generated square wave is output on OP3 if it is programmed to be the C/T output. In the counter mode,

the value C/T loaded into CTPU and CTPL by the CPU is counted down to 0. Counting begins upon

receipt of a start counter command. Upon reaching terminal count 0x0000, the counter ready interrupt bit

(ISR[3]) is set. The counter continues counting past the terminal count until stopped by the CPU. If OP3 is

programmed to be the output of the C/T, the output remains HIGH until terminal count is reached, at which

time it goes LOW. The output returns to the HIGH state and ISR[3] is cleared when the counter is stopped

by a stop counter command. The CPU may change the values of CTPU and CTPL at any time, but the

new count becomes effective only on the next start counter commands. If new values have not been

loaded, the previous count values are preserved and used for the next count cycle.

In the counter mode, the current value of the upper and lower 8 bits of the counter (CTU, CTL) may be

read by the CPU. It is recommended that the counter be stopped when reading to prevent potential

problems which may occur if a carry from the lower 8 bits to the upper 8 bits occurs between the times

that both halves of the counter are read. However, note that a subsequent start counter command will

cause the counter to begin a new count cycle using the values in CTPU and CTPL.

When the C/T clock divided by 16 is selected, the maximum divisor becomes 1,048,575.

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