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TL28L92 bảng dữ liệu(PDF) 7 Page - Texas Instruments

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tên linh kiện TL28L92
Giải thích chi tiết về linh kiện  3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter
PDF  61 Pages
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Trang chủ  http://www.ti.com
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TL28L92 bảng dữ liệu(HTML) 7 Page - Texas Instruments

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1.2.1 Device Information
TL28L92 (80xxx mode)
8
BUS BUFFER
CHANNEL B
(AS ABOVE)
D0 to D7
OPERATION
CONTROL
ADDRESS
DECODE
R/W CONTROL
RESET
I/M
open or connect
to VCC for 80xxx
A0 to A3
CEN
WRN
RDN
4
INTERRUPT
CONTROL
IMR
ISR
GP
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL
OSCILLATOR
CSRA
CSRB
ACR
CTL
CTU
INTRN
X2
X1/CLK
CHANNEL A
16-BYTE
TRANSMIT FIFO
TRANSMIT
SHIFT REGISTER
16-BYTE
RECEIVE FIFO
WATCHDOG
TIMER
TxDA
RxDA
RxDB
RECEIVE
SHIFT REGISTER
MRA0, 1, 2
CRA
SRA
INPUT PORT
CHANGE-OF-
STATE
DETECTORS (4)
ACR
IPCR
IP0 to IP6
7
TxDB
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPR
OPCR
OP0 to OP7
8
TL28L92
3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter
www.ti.com
SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008
A.
The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic
0 (LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark
usually means inactive and Space means active. The voltage levels represented by the terms Mark and Space are
often reversed from those above: Mark is low voltage, and Space is high voltage.
Figure 1-1. Block Diagram (80xxx Mode)
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General Description
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