TL28L92 datasheet(26/61 Pages) TI

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3.3

3.3.1

Mode Registers

3.3.1.1 Mode Register 0 Channel A (MR0A)

TL28L92

3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008

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Table 3-19. Output Port Configuration Register (OPCR)(1)

configure OP7

configure OP6

configure OP5

configure OP4

configure OP3

configure OP2

configure OP1

configure OP0

(1)

OP1 and OP0 are the RTSN output and are controlled by the MR register

Table 3-20. Mode Register 0 Channel A (MR0A) (Address 0x0) Bit Allocation(1)

BAUDRATE

RxWATCHDOG

RxINT[2]

TxINT[1:0]

FIFOSIZE

TEST2

EXTENDED II

EXTENDED I

(1)

MR0 is accessed by setting the MR pointer to logic 0 via the command register command B.

Table 3-21. Mode Register 0 Channel A (MR0A) (Address 0x0) Bit Description

BIT(S)

SYMBOL

DESCRIPTION

RxWATCHDOG

This bit controls the receiver watchdog timer.

0 = disable

1 = enable

When enabled, the watchdog timer will generate a receiver interrupt if the receiver FIFO has not been

accessed within 64 bit times of the receiver 1

× clock. The watchdog timer is used to alert the control

processor that data is in the Rx FIFO that has not been read. This situation will occur when the byte count

of the last part of a message is not large enough to generate an interrupt. The watchdog timer presents

itself as a receiver interrupt with the RxRDY bit set in SR and ISR.

RxINT[2]

Bit 2 of receiver FIFO interrupt level. This bit along with bit 6 of MR1 sets the fill level of the FIFO that

generates the receiver interrupt. Note that this control is split between MR0 and MR1. This is for

backward compatibility to the SC2692. For the receiver these bits control the number of FIFO positions

filled when the receiver will attempt to interrupt. After the reset the receiver FIFO is empty. The default

setting of these bits cause the receiver to attempt to interrupt when it has one or more bytes in it; see

Table 3-22

5 and 4

TxINT[1:0]

Transmitter interrupt fill level. For the transmitter these bits control the number of FIFO positions empty

when the receiver will attempt to interrupt; see Table 3-23. After the reset the transmit FIFO has 8 bytes

empty. It will then attempt to interrupt as soon as the transmitter is enabled. The default setting

(TxINT[1:0] = 00) condition the transmitter to attempt to interrupt only when it is completely empty. As

soon as one byte is loaded, it is no longer empty and hence will withdraw its interrupt request.

FIFOSIZE

FIFO size for channel A and channel B. Selects the FIFO depth at 8-byte or 16-byte.

0 = 8 bytes

1 = 16 bytes

BAUDRATE

Bits MR0[2:0] are used to select one of the six baud rate groups. See Table 3-32 for the group

EXTENDED I

organization.

TEST2

000 = Normal mode

BAUDRATE

001 = Extended mode I

EXTENDED II

100 = Extended mode II

Other combinations of MR0[2:0] should not be used.

Programming

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