TL28L92 datasheet(41/61 Pages) TI

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3.3.12 Interrupt Mask Register (IMR)

TL28L92

3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

www.ti.com

SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008

Table 3-55. Interrupt Status Register (ISR) (Address 0x5) Bit Description

BIT(S)

SYMBOL

DESCRIPTION

–

Input port change status.

0 = not active

1 = active

This bit is a logic 1 when a change of state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event

has been selected to cause an interrupt by the programming of ACR[3:0]. The bit is cleared when the CPU

reads the IPCR.

–

Channel B change in break.

0 = not active

1 = active

This bit, when set, indicates that the channel B receiver has detected the beginning or the end of a received

break. It is reset when the CPU issues a channel B reset break change interrupt command.

RxRDYB

RxB interrupt.

0 = not active

1 = active

This bit indicates that the channel B receiver is interrupting according to the fill level programmed by the

MR0 and MR1 registers or the watchdog timer has timed-out. This bit has a different meaning than the

receiver ready/full bit in the status register.

TxRDYB

TxB interrupt.

0 = not active

1 = active

This bit indicates that the channel B transmitter is interrupting according to the interrupt level programmed in

the MR0[5:4] bits. This bit has a different meaning than the TxRDY bit in the status register.

–

Counter ready.

0 = not active

1 = active

In the counter mode, this bit is set when the counter reaches terminal count and is reset when the counter is

stopped by a stop counter command. In the timer mode, this bit is set once each cycle of the generated

square wave (every other time that the counter/timer reaches zero count). The bit is reset by a stop counter

command. The command, however, does not stop the counter/timer.

–

Channel A change in break.

0 = not active

1 = active

This bit, when set, indicates that the channel A receiver has detected the beginning or the end of a received

break. It is reset when the CPU issues a channel A reset break change interrupt command.

RxRDYA

RxA interrupt.

0 = not active

1 = active

This bit indicates that the channel A receiver is interrupting according to the fill level programmed by the

MR0 and MR1 registers or the watchdog timer has timed-out. This bit has a different meaning than the

receiver ready/full bit in the status register.

TxRDYA

TxA interrupt.

0 = not active

1 = active

This bit indicates that the channel A transmitter is interrupting according to the interrupt level programmed in

the MR0[5:4] bits. This bit has a different meaning than the TxRDY bit in the status register.

The programming of this register selects which bits in the ISR causes an interrupt output. If a bit in the

ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1 the INTRN output will be asserted. If

the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN

output. Note that the IMR does not mask the programmable interrupt outputs OP3 to OP7 or the reading

of the ISR.

Table 3-56. Interrupt Mask Register (IMR) (Address 0x5) Bit Allocation

input port

change break

RxRDYB

RxRDYA

TxRDYB

counter ready

change break A

TxRDYA

change

FFULLB

FFULLA

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