TL28L92 datasheet(44/61 Pages) TI

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3.4

Output Port Notes

3.5

CTS, RTS, CTS Enable Tx Signals

TL28L92

3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008

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The output ports are controlled from four places: the OPCR register, the OPR register, the MR registers

and the command register. The OPCR register controls the source of the data for the output ports OP2 to

OP7. The data source for output ports OP0 and OP1 is controlled by the MR and CR registers. When the

OPR is the source of the data for the output ports, the data at the ports is inverted from that in the OPR

The content of the OPR register is controlled by the Set Output Port bits command and the Reset Output

Port bits command. These commands are at 0xE and 0xF, respectively. When these commands are used,

action takes place only at the bit locations where ones exist. For example, a logic 1 in bit location 5 of the

data word used with the Set Output Port bits command will result in OPR5 being set to one. The OP5

would then be set to logic 0 (VSS). Similarly, a logic 1 in bit position 5 of the data word associated with the

Reset Output Ports bits command would set OPR5 to logic 0 and, hence, the pin OP5 to a logic 1 (VDD).

Clear To Send (CTS) is usually meant to be a signal to the transmitter meaning that it may transmit data

to the receiver. The CTS input is on pin IP0 for TxA and on IP1 for TxB. The CTS signal is active LOW;

thus, it is called CTSAN for TxA and CTSBN for TxB. RTS is usually meant to be a signal from the

receiver indicating that the receiver is ready to receive data. It is also active LOW and is, thus, called

RTSAN for RxA and RTSBN for RxB. RTSAN is on pin OP0 and RTSBN is on OP1. A receiver’s RTS

output will usually be connected to the CTS input of the associated transmitter. Therefore, one could say

that RTS and CTS are different ends of the same wire.

MR2[4] is the bit that allows the transmitter to be controlled by the CTS pin (IP0 or IP1). When this bit is

set to one AND the CTS input is driven HIGH, the transmitter will stop sending data at the end of the

present character being serialized. It is usually the RTS output of the receiver that will be connected to the

transmitter’s CTS input. The receiver will set RTS HIGH when the receiver FIFO is full AND the start bit of

the 9th or 17th character is sensed. Transmission then stops with 9 or 17 valid characters in the receiver.

When MR2[4] is set to one, CTSN must be at zero for the transmitter to operate. If MR2[4] is set to zero,

the IP pin will have no effect on the operation of the transmitter. MR1[7] is the bit that allows the receiver

to control OP0. When OP0 (or OP1) is controlled by the receiver, the meaning of that pin will be.

Programming

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