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M38063M2AFP bảng dữ liệu(PDF) 26 Page - Renesas Technology Corp |
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M38063M2AFP bảng dữ liệu(HTML) 26 Page - Renesas Technology Corp |
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26 / 58 page ![]() 25 MITSUBISHI MICROCOMPUTERS 3806 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D Converter The functional blocks of the A-D converter are described below. [A-D conversion register] The A-D conversion register is a read-only register that stores the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. [AD/DA control register] The AD/DA control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. Bits 6 and 7 are used to control the output of the D-A converter. [Comparison voltage generator] The comparison voltage generator divides the voltage between AVSS and VREF into 256, and outputs the divided voltages. [Channel selector] The channel selector selects one of the ports P60/AN0 to P67/AN7, and inputs the voltage to the comparator. Fig.18 Structure of AD/DA control register Fig. 19 Block diagram of A-D converter [Comparator and Control circuit] The comparator and control circuit compares an analog input volt- age with the comparison voltage, then stores the result in the A-D conversion register. When an A-D conversion is complete, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(XIN) to 500 kHz or more during an A-D conversion. AD/DA control register (ADCON : address 003416) Analog input pin selection bits 0 0 0: P60/AN0 0 0 1: P61/AN1 0 1 0: P62/AN2 0 1 1: P63/AN3 1 0 0: P64/AN4 1 0 1: P65/AN5 1 1 0: P66/AN6 1 1 1: P67/AN7 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (return "0" When read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled b7 b0 b2 b1 b0 A-D control circuit A-D conversion register Resistor ladder VREF AVSS Comparator A-D interrupt request b7 b0 3 8 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 Data bus (Address 0035 16) AD/DA control register (Address 0034 16) |
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