M38063M2AFP datasheet(18/58 Pages) RENESAS

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MITSUBISHI MICROCOMPUTERS

3806 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timers

The 3806 group has four timers: timer X, timer Y, timer 1, and

timer 2.

All timers are count down. When the timer reaches “0016”, an un-

derflow occurs at the next count pulse and the corresponding

timer latch is reloaded into the timer and the count is continued.

When a timer underflows, the interrupt request bit corresponding

to that timer is set to “1”.

The division ratio of each timer or prescaler is given by 1/(n + 1),

where n is the value in the corresponding timer or prescaler latch.

Timer 1 and Timer 2

The count source of prescaler 12 is the oscillation frequency di-

vided by 16. The output of prescaler 12 is counted by timer 1 and

timer 2, and a timer underflow sets the interrupt request bit.

Timer X and Timer Y

Timer X and Timer Y can each be selected in one of four operating

modes by setting the timer XY mode register.

Timer Mode

The timer counts f(XIN)/16 in timer mode.

Pulse Output Mode

Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of

the timer reach “0016”, the signal output from the CNTR0 (or

CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge

switch bit is “0”, output begins at “ H”.

If it is “1”, output starts at “L”. When using a timer in this mode, set

the corresponding port P54 ( or port P55) direction register to out-

put mode.

Event Counter Mode

Operation in event counter mode is the same as in timer mode,

except the timer counts signals input through the CNTR0 or

CNTR1 pin.

Pulse Width Measurement Mode

If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer

counts at the oscillation frequency divided by 16 while the CNTR0

(or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge

switch bit is “1”, the count continues during the time that the

CNTR0 (or CNTR1) pin is at “L”.

In all of these modes, the count can be stopped by setting the

timer X (timer Y) count stop bit to “1”. Ever y time a timer

underflows, the corresponding interrupt request bit is set.

Fig. 8 Structure of timer XY register

Timer X count stop bit

0: Count start

1: Count stop

Timer XY mode register

(TM : address 002316)

Timer Y operating mode bit

0 0: Timer mode

0 1: Pulse output mode

1 0: Event counter mode

1 1: Pulse width measurement mode

CNTR1 active edge switch bit

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

CNTR0 active edge switch bit

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

Timer X operating mode bit

0 0: Timer mode

0 1: Pulse output mode

1 0: Event counter mode

1 1: Pulse width measurement mode

b1b0

b5b4

Timer Y count stop bit

0: Count start

1: Count stop

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