MSC8122VT8000 datasheet(18/48 Pages) FREESCALE

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MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Electrical Characteristics

Freescale Semiconductor

In all cases, the power-up sequence must follow the guidelines shown in Figure 8.

The following rules apply:

During time interval A, VDDH should always be equal to or less than the VDD/VCCSYN voltage level.

The duration of interval A should be kept below 10 ms.

The duration of timing interval B should be kept as small as possible and less than 10 ms.

2.5.3

Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for

internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum

frequency values are not exceeded.

Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN

Table 7. Maximum Frequencies

Characteristic

Maximum in MHz

Core frequency

300/400/500

Reference frequency (REFCLK)

100/133/166

Internal bus frequency (BLCK)

100/133/166

DSI clock frequency (HCLKIN)

•

Core frequency = 300 MHz

•

Core frequency = 400/500 MHz

HCLKIN

≤ (min{70 MHz, CLKOUT})

HCLKIN

≤ (min{100 MHz, CLKOUT})

External clock frequency (CLKIN or CLKOUT)

100/133/166

Table 8. Clock Frequencies

Characteristics

Symbol

300 MHz Device

400 MHz Device

500 MHz Device

Min

Max

Min

Max

Min

Max

CLKIN frequency

FCLKIN

100

133.3

166.7

BCLK frequency

FBCLK

100

133.3

166.7

Reference clock (REFCLK) frequency

FREFCLK

100

133.3

166.7

Output clock (CLKOUT) frequency

FCLKOUT

100

133.3

166.7

SC140 core clock frequency

FCORE

200

300

200

400

200

500

Note:

The rise and fall time of external clocks should be 3 ns maximum

3.3 V

1.2 V

VDD/VCCSYN

VDDH (IO)

t (time)

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