MSC8122VT8000 datasheet(39/48 Pages) FREESCALE

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MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Freescale Semiconductor

Hardware Design Considerations

The following sections discuss areas to consider when the MSC8122 device is designed into a system.

3.1

Start-up Sequencing Recommendations

Use the following guidelines for start-up and power-down sequences:

•Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the

required minimum power levels. This can be implemented via weak pull-down resistors.

•

CLKIN

can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must

start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels.

•

If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up

VDDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring both

voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down first and

then VDD/VCCSYN.

Note:

This recommended power sequencing for the MSC8122 is different from the MSC8102. See Section 2.5.2 for

start-up timing specifications.

External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time, including during

power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.

This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the

system during start-up.

During the power-up sequence, if VDD rises before VDDH (see Figure 6), current can pass from the VDD supply through the

device ESD protection circuits to the VDDH supply. The ESD protection diode can allow this to occur when VDD exceeds VDDH

by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:

Figure 31. Test Access Port Timing Diagram

Figure 32. TRST Timing Diagram

TCK

(Input)

TDI

(Input)

TDO

(Output)

TDO

(Output)

VIH

VIL

Input Data Valid

Output Data Valid

TMS

708

709

710

711

TCK

(Input)

TRST

(Input)

713

712

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