Hardware Design Considerations

MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Freescale Semiconductor

41

by a 0.01-µF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of

the PCB aligned with the depopulated void on the MSC8122 located in the square defined by positions, L11, L12, L13, M11,

M12, M13, N11, N12, and N13.

3.3

Connectivity Guidelines

Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to

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disconnected.

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up or down, depending on design requirements.

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HDST

can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the

DCR[DSRFA] bit is set.

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HDBE[1–3]

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must be pulled up.

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When the DSI uses sliding window address mode (DCR[SLDWA] = 1), the external HA[11–13] signals must be

connected (tied) to the correct voltage levels so that the host can perform the first access to the DCR. After reset, the

DSI expects full address mode (DCR[SLDWA] = 0). The DCR address in the DSI memory map is 0x1BE000, which

requires the following connections:

— HA11 must be pulled high (1)

— HA12 must be pulled high (1)

— HA13 must be pulled low (0)

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In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):

functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.

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If there is an external bus master (BCR[EBM] = 1):

functionality.

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modes, they must be pulled up.

0.01 µF

10 µF

10

Ω

10nH