MSC8122VT8000 datasheet(26/48 Pages) FREESCALE

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MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Electrical Characteristics

Freescale Semiconductor

2.5.5.2

CLKIN to CLKOUT Skew

Table 17 describes the CLKOUT-to-CLKIN skew timing.

For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing

values specified for CLKIN synchronization. Figure 12 shows the relationship between the CLKOUT and CLKIN timings.

Table 16. CLKOUT Skew

No.

Characteristic

Min1

Max1

Units

Rise-to-rise skew

•VDD = 1.1 V

•VDD = 1.2 V

0.0

0.95

0.85

Fall-to-fall skew

•VDD = 1.1 V

•VDD = 1.2 V

–1.5

–0.8

1.0

CLKOUT phase (1.2 V, 133 MHz)

•

Phase high

•

Phase low

2.8

—

CLKOUT phase (1.1 V, 133 MHz)

•

Phase high

•

Phase low

2.2

—

CLKOUT phase (1.1 V, 100 MHz)

•

Phase high

•

Phase low

3.3

—

Notes:

A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.

Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.

CLKOUT skews are measured using a load of 10 pF.

CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.

Figure 12. CLKOUT and CLKIN Signals.

CLKIN

CLKOUT

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