MSC8122VT8000 datasheet(27/48 Pages) FREESCALE

tên linh kiện	MSC8122VT8000

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Electrical Characteristics

MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Freescale Semiconductor

2.5.5.3

DMA Data Transfers

Table 17 describes the DMA signal timing.

The DREQ

signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ

according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction.

Table 17. DMA Signals

No.

Characteristic

Ref = CLKIN

Ref = CLKOUT

(1.2 V only)

Units

Min

Max

Min

Max

DREQ set-up time before the 50% level of the falling edge of REFCLK

5.0

—

5.0

—

DREQ hold time after the 50% level of the falling edge of REFCLK

0.5

—

0.5

—

DONE set-up time before the 50% level of the rising edge of REFCLK

5.0

—

5.0

—

DONE hold time after the 50% level of the rising edge of REFCLK

0.5

—

0.5

—

DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge

0.5

7.5

0.5

8.4

Figure 13. DMA Signals

REFCLK

DREQ

DONE

DACK/DONE/DRACK

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