ST20-C1 datasheet(52/205 Pages) STMICROELECTRONICS

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4.11 Peripherals and I/O

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4.10.5 Other work space allocation techniques

The

gajw instruction exchanges the contents of Wptr and Areg, allowing work spaces

to be allocated dynamically, and allowing dynamic switching between existing work

spaces. If a process work space holds a pointer to a new work space, then the

following code changes to the new work space and stores a pointer to the old work

space.

ldl Wnew; gajw; stl Wold;

The old work space can be restored by

ldl Wold; gajw;

In addition, the old work space can be accessed from the new work space, using

ldl Wold; ldnl x;

ldl Wold; stnl x;

ldl Wold; ldnlp x;

4.11 Peripherals and I/O

The peripheral and I/O instructions are listed in Table 4.13.

4.11.1 Using the IO register

The IO register is a 32-bit register used for simple bit control of devices outside the

core. The bits of the register are directly mapped to external connections on the ST20-

C1 core. The connections to and from the IO register may be to on-chip or external

peripherals depending on the particular chip design. The bits of the IO register are

defined in Table 3.3. Some bits at the most significant end of each half word may be

reserved for the system in some ST20 variants; see the data sheet for the variant.

Setting an output bit will cause the corresponding connection to be driven high, and

clearing the bit will drive the connection low. Similarly any input or output bit may be

tested for the state of the connection; if the connection is high the bit will be set and if

the connection is low the bit will be clear.

The instruction

io sets and clears bits of the IO register and loads a copy of the initial

IO register. A bit in the bottom half-word may be set in the IO register by:

ldc 0; ldc bit_number; bitmask; io;

A bit in the bottom half-word may be cleared in the IO register by:

ldc bit_number; bitmask; ldc 0; io;

Mnemonic

Name

input / output

bitmask

bit mask

ldtdesc

load task descriptor

stop

stop process

Table 4.13 Peripheral and I/O instructions

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